One or more embodiments relate to a nonvolatile memory device and, more particularly, to a nonvolatile memory device and a method of operating the same and a control device for controlling the same, which is configured to program data, decoded using actual data and random data, when a program or read operation is performed.
Flash memory, that is, nonvolatile memory is chiefly divided into NAND flash memory and NOR flash memory. NOR flash memory has an excellent random access time characteristic because it has a structure in which memory cells are independently connected to respective bit lines and respective word lines. NAND flash memory is excellent in terms of the integration level because it has a structure in which memory cells are connected in series, requiring only one contact per cell string. Accordingly, the NAND structure is for the most part used in highly-integrated flash memory.
Recently, in order to further increase the integration of flash memory, active research has been done on a multi-bit cell which is capable of storing plural data in one memory cell. This type of a memory cell is generally called a Multi-Level Cell (MLC). A memory cell capable of storing a single bit is called a Single Level Cell (SLC).
The MLC has cell voltage levels in order to store plural bits of data, as described above. Using the cell voltage levels, different data is stored depending on respective cell voltages.
FIG. 1 is a diagram showing the construction of the memory cell array of a nonvolatile memory device formed by conventional methods.
Referring to FIG. 1, the memory cell array 110, including memory cells of the nonvolatile memory device, includes cell strings. Furthermore, each of the cell strings is connected to a bit line BL.
Each of the cell strings has a construction in which memory cells C are connected in series between a Drain Select Transistor (DST) and a Source Select Transistor (SST).
The gates of the memory cells are connected to respective word lines WL, which are configured to intersect the bit lines BL. The memory cell array 110 of FIG. 1 includes first to 32th word lines WL<0> to WL<31>.
Assuming that a word line selected for program (indicated by “sel”) is the 30th word line WL<29>, the remaining word lines are unselected word lines (indicated by “unsel”).
A page buffer 120 is connected to each pair of the bit lines. In the case where the 30th word line WL<29> of the memory cell array 110 is programmed, a program voltage is applied to the 30th word line WL<29> and a pass voltage is applied to the remaining word lines.
Here, if the memory cells C are MLCs, each of the memory cells stores plural bits. Thus, threshold voltages for distinguishing between different stored bits during a read operation may be changed depending on whether or not the cells of a string neighboring the memory cells have been programmed (Back Pattern Dependency (hereinafter referred to as ‘BPD’)).
In order to reduce this BPD, a method of performing an actual program operation from the first word line WL<0> to the 32th word line WL<31> in sequence is used.
FIG. 2 illustrates the distributions of threshold voltages of memory cells resulting from BPD.
Referring to FIG. 2, the distributions of threshold voltages of memory cells may be widened because the memory cells are over programmed (OP) or under programmed (UP) due to the influence of surrounding programmed memory cells. If the distributions of threshold voltages distinguishing different bits are widened, a problem arises because, when the threshold voltages have plural distribution states as in a MLC, a margin between the threshold voltages is narrowed.
If, in order to reduce the problem of BPD, a pass voltage applied to an unselected word line to which programmed memory cells are connected is excessively raised, a disturbance phenomenon, where unwanted memory cells are programmed, may occur.